Over the years, integrated circuit technology has steadily advanced so that various integrated circuit technology has penetrated the very fabric of our daily work, home, leisure, and recreation environments. As application and uses of integrated circuit technology have increased steadily, a demand for lower and lower power consumption, more and more functional capacity within a small area, and higher and higher quality products have likewise continued to increase. Accordingly, low power integrated circuit technology, such as complimentary metal oxide semiconductor ("CMOS"), has become more widespread.
Some of the low power integrated circuits, e.g., CMOS technology, include circuits or devices which consume little or no power and are known as "zero power" devices. Examples of zero power integrated circuit modules can be seen in U.S. Pat. Nos. 5,089,877 and 5,008,776 by Queyssac et al. and which are also assigned to the common assignee of the present application.
A problem, however, has developed with some low power or zero power devices, e.g., asynchronous static random access memory ("SRAM") devices, whereby accidental entry into "sleep mode" can occur. Sleep mode is a mode of operation in which a memory array and an oscillator, for example, of the device are disconnected from the power supply. For example, the memory array may have a p-channel switch which can be switched off when in a sleep mode. The sleep mode allows the primary contributors to battery current (e.g., a memory array (polysilicon resistor) and a clock oscillator) to be switched off. This is particularly useful when the battery is attached to the device during assembly.
During battery attach, for example, it can be useful to have the device automatically go into sleep mode as the battery is attached. Then the battery voltage can be measured to verify continuity and that no shorts exist across the battery. If not for the sleep mode, it can be hard to distinguish normal battery current (including the memory array and the oscillator) from some low level continuity problem.
As external power or V.sub.CC is applied to the device during post-battery attach testing, the device exits sleep mode as external power or V.sub.CC exceed the battery voltage. Then the memory array can be exercised. At the end of testing (and before the device is shipped), a register is written to place the device back into sleep mode. Thus, there is no appreciable drain on the battery before the customer is ready to use the device. Once the customer finally applies external power or V.sub.CC to the device, and it exceeds the battery voltage, the device exits sleep mode and operates normally. There is no further need to enter sleep mode from this point on, and the user has no means to put the device in sleep mode. As can be seen, devices sitting on the shelf prior to use by the customer generally experience no degradation in battery life.
Nevertheless, in some environments, the sleep mode circuitry can be corrupted. This can cause some devices to be accidentally placed in sleep mode and destroy data in the memory array. Sometimes, for example, pins may go below a reference or ground voltage or V.sub.SS for relatively long periods of time. This can forward bias parasitic diodes and/or bipolar transistors and pull down the battery voltage seen by the device. Once this undershoot condition goes away, the battery voltage which is switched into the device will return to its original value. This situation can look like a battery attach event, and the circuitry can cause sleep mode to be entered again. Alternatively, latches storing the sleep mode as a non-sleep mode state can become corrupted. Also, in this situation, power to the memory array can be disconnected and data can be corrupted or destroyed.